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The logos can be opened with Adobe Illustrator, Macromedia Freehand, CorelDraw or Adobe Photoshop. All the logos are also available in format EPS.
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.............................. Intel Pentium 3
Logo and Trademark..............................
The Pentium III brand refers to Intel's 32-bit x86 desktop and mobile microprocessors (with the sixth-generation Intel P6 microarchitecture) introduced on February 26, 1999 and containing 9.5 million transistors. The brand's initial processors were very similar to the earlier CPUs branded Pentium II. The most notable difference was the addition of the SSE instruction set (to accelerate media processing and 3D graphics), and the introduction of a controversial serial number embedded in the chip during the manufacturing process.
Similarly to the Pentium II it superseded, the Pentium III was also accompanied by the Celeron brand for lower-end CPU versions, and the Xeon for high-end (server and workstation) derivatives. The Pentium III was eventually superseded by the Pentium 4, but its Tualatin core also served as the basis for the Pentium M CPUs, which used many ideas from the Intel P6 microarchitecture. Subsequently, it was the P-M microarchitecture of Pentium M branded CPUs, and not the NetBurst found in Pentium 4 processors, that formed the basis for Intel's energy-efficient Intel Core microarchitecture of CPUs branded Core 2, Pentium Dual-Core, Celeron (Core), and Xeon. The Pentium III was the first Intel processor to break 1 GFLOPS, with a theoretical performance of 2 GFLOPS.
Since Katmai was built in the same 0.25 µm process as Pentium II "Deschutes", it had to implement SSE using as little silicon as possible. To achieve this goal, Intel implemented the 128-bit architecture by double-cycling the existing 64-bit data paths and by merging the SIMD-FP multiplier unit with the x87 scalar FPU multiplier into a single unit. To utilize the existing 64-bit data paths, Katmai issues each SIMD-FP instruction as two μops. To compensate partially for implementing only half of SSE’s architectural width, Katmai implements the SIMD-FP adder as a separate unit on the second dispatch port. This organization allows one half of a SIMD multiply and one half of an independent SIMD add to be issued together bringing the peak throughput back to four floating point operations per cycle — at least for code with an even distribution of multiplies and adds.
The issue was that Katmai’s hardware-implementation contradicted the parallelism model implied by the SSE instruction-set. Programmers faced a code-scheduling dilemma: Should the SSE-code be tuned for Katmai's limited execution resources, or should it be tuned for a future processor with more resources? Katmai-specific SSE optimizations yielded the best possible performance from the Pentium III family, but was suboptimal for later Intel processors, such as the Pentium 4 and Core.
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